Buried insulator substrates, such as silicon-on-insulator (SOI) substrates, have become desirable for many microelectronic technologies, including extreme scaling of metal-oxide semiconductor (MOS) and complementary metal-oxide semiconductor (CMOS) devices, advanced MOS junction-type field-effect transistors (MOSFETs), and quantum wires and dots. This is primarily because SOI fabrication processes result in increased packing densities, improved performances, better device isolations and reduced extrinsic parasitic elements, particularly those of the source and drain as well as leakage currents and thus significantly speeding up circuit operations.
An insulator layer within a buried insulator substrate may suppress performance-reducing, and therefore undesirable drain-induced barrier lowering (DIBL) effects in the channel region. The thinner the insulator layer, the more DIBL is reduced and the more drain current performance improves. Unfortunately, as the insulator layer is made thinner, the area capacitance increases, which degrades switching performance. This higher area capacitance causes more coupling between the immediate device and other neighboring devices through the substrate, which leads to undesirable cross-talk or interference between adjacent devices which should be isolated from each other. There is a need for a solution which allows for a very thin insulator layer and therefore high DIBL reduction, while also counteracting the increased area capacitance concomitant with thinner insulator layers.